Graduate Researcher: Dan Kollmann
February 2003
Although Low Temperature Co-fired Ceramic (LTCC) is a relatively young substrate technology, it is already showing promise for use in wireless applications covering the 1-40 GHz frequency range. LTCC consists of multiple thin layers, which are stacked vertically and then co-fired to become a hermetically sealed substrate (or package). Prior to stacking, circuits are printed on the individual layers. Through the use of vias punched and metal filled through one or more layers, a circuit designer has the ability to create 3-dimensional (3-D) circuits, which inherently use less space than their 2-D counterparts. LTCC has already proven to be a cost efficient and space saving method for high-performance low frequency (<2 GHz) designs.
In order to take advantage of the benefits of embedded and 3-D high frequency (1-40 GHz) circuits, a designer should have access to models describing the behavior of all components used within a system. This research seeks to develop vertical transition models for coplanar waveguide (CPW) configurations in embedded substrates. Wideband operation is sought and lumped element models are being developed for 40 GHz bandwidth operation.
Graduate Researcher: Emile Davies-Venn
February 2003
The prevalence of integrated circuits for compact system design requires novel design approaches. High dielectric constant materials in high frequency integrated microelectronics circuits (GHz) has and continues to limit the efficiency of structures that include antennae and lumped element interconnects.
This research examines methods of obtaining the low dielectric index material required for improving such structure using the high index material used in most integrated circuits. Novel substrate configurations are researched that combine low and high dielectric material. A variety of planar geometries are studied and performance metrics are being determined. Preliminary results show certain configurations can result in index reduction as low as 20% of the original material index.
Graduate Researcher: S. Riki Banerjee
February 2003
Combining the high-speed data communications with telecommunications technology requires new design methods that integrate RFIC designs used for electronic drive circuits with high data rate optoelectronic components. A subsequent need is to develop advanced packaging methods that are complementary to chip-level electronic and photonic packaging. The features of the integrated package design should offer integration capability of compact circuits onto high dielectric constant materials and leverage the advantage of low cost monolithic fabrication processes.
This work focuses on the development of suitable wideband interconnects for integrated packages. Low dispersion is sought as well as approaches that minimize crosstalk between proximate signal lines. A variety of micromachined configurations are being explored using traditional microstrip and coplanar architectures. Interconnects in single or array designs are being studied in silicon optical microbench technology used in optoelectronic applications such as vertical cavity surface emitting lasers (VCSELs). Integrated package designs based on the aforementioned configurations are also being investigated along with methods to improve high speed testing of electric signal lines.
Graduate Researcher: Isaac Itotia
February 2003
Porous silicon has the to potential to allow the integration of IC and RF technologies on a single substrate. Additionally this material is complementary to post-processing of CMOS and MEMs fabrication. Understanding its high frequency behavior can provide an important bridge in our current knowledge of this material at RF frequencies.
This research investigates the effect of material properties such as porosity, thickness, doping, and bulk substrates on high frequency circuit performance. Transmission line properties on CPW are being studied to develop comprehensive understanding of this material for high frequency applications. Preliminary results have shown that using porous silicon on an underlying low resistivity substrates the attenuation on these substrates can be significantly reduced from about 20 dB/cm for the low resistivity substrates to about 5 dB/cm (at 50 GHz) thus brining its attenuation closer to that of high resistivity silicon. This in turn provides one with a substrate that can be used in the integration of IC and RF circuits.
Figure: Cross sectional view of a CPW on porous silicon with an underlying bulk substrate along with a scanning electron microscope (SEM) picture of a fabricated sample
Graduate Researcher: Can Eyup Akgun
January 2003
As integrated circuit technologies continue to increase, there is a desire to extract the electrical properties of materials. Resonator structures have offered a useful means for acquiring these material properties. Conventional microstrip topologies have produced accurate characterization up to 40 GHz. In hybrid circuits, Coplanar Waveguide (CPW) topologies have become another option to the conventional microstrip topologies in microwave integrated circuits (MICs) and monolithic microwave integrated circuits (MMICs). Coplanar Waveguide designs offer lower substrate height dependence and less sensitivity to impedance changes, thus, presenting a more consistent extraction method for extracting dielectric property information. As a result, CPW planar resonators are investigated to determine wideband material properties, such as attenuation and dielectric constant.
A variety of CPW resonators are being investigated theoretically and experimentally for “T” and ring-resonator designs. In “T” resonator designs, various configurations and terminations are studied to minimize edge coupling and suppress higher order modes. Ring-resonator designs are investigated to reduce open end and curvature effects. Feeding architectures are also being evaluated to optimize signal coupling with minimum loading.